Non-volatile memory (“NVM”) cells are fabricated in a large variety of structures, including but not limited to the Nitride Read Only Memory (“NROM”), as shown in FIG.1. Until recently, NVM cells were primarily fabricated as “floating gate” devices, where charge could be injected into a conducting charge storage layer (e.g. poly-silicon) sandwiched between two insulation layers (e.g. silicon-oxide), and the injected charge could freely migrate across the charge storage layer. More recently, improved NVM cells such as the one shown in FIG. 1 and methods for their operation have been devised, such that the charge storage layer is composed of a dielectric, rather than a conducting material, and resulting in the possibility to store charges in multiple charge storage regions of a single charge storage layer, thereby increasing the number of logical values which may be stored on a single NVM device. As will be explained further below, although the improved multi-charge storage region devices have enhanced data storage capacity, they are susceptible to data corruption due to a variety of effects related to the operation of neighboring cells or devices.
Generally, the logical state of an NVM cell is defined by its threshold voltage (“VT”), the voltage value which when applied to the NVM cell's gate populates the cell's channel with a sufficient number of charge carriers to enable the cell's channel to conduct current. In cases where the NVM cell is a multi-charge storage region device, each charge storage/trapping region may have its own associated VT, where the VTfor a given charge storage/trapping region may be defined as the voltage that when applied to the gate terminal of the device causes sufficient numbers of carriers near the Source, to populate a segment of the device's channel, near and beneath the charge storage region, so as to allow current to flow through the given channel segment. With most multi-charge storage devices, the charge storage regions are located on either side of the storage layer, and their respective channel segments are located beneath the charge storage regions, very near the junctions on either end of the channel. Various methods for operating (e.g. programming, reading and erasing) an NVM cells is known, but generally a cell's or a charge storage region's (as in the case of multi-charge storage region devices) VT, which defines a logical state, is regulated by either injecting or removing charge from it's the relevant charge storage/trapping region.
FIG. 2A shows a voltage distribution graph depicting a correlation between an exemplary NVM cell's (from this point onward, the term cell will also apply to the each charge storage regions of a multi-charge storage region's cell) voltage threshold level and the exemplary cell's logical state. The threshold voltage distribution shown is for a binary non-volatile memory cell, wherein vertical lines of the graph depict boundary threshold voltage values between the binary NVM cell's possible logical states. For example: (1) when the cell's threshold voltage is determined to be below an Erase Verified (“EV”), voltage level, the cell's logical state is “Erased”(e.g. logical “1”); (2) when the cell's threshold voltage level is above a Program Verified (“PV”) voltage level, the cell's logical state is “Programmed (e.g. logical “0”). Due to various phenomena that may cause the threshold voltage of a cell to fluctuate, up or down, other intermediate threshold levels, such as a Read Verify (“RV”) level, may be used during the reading of an NVM cell. More specifically, when the cell's threshold voltage level is above a RV voltage level, the cell's logical state may be considered “programmed” (e.g. logical “0”) and when the cell's threshold voltage level is below the RV level, the cell's logical state may be considered non-programmed or erased (e.g. logical “1”).
FIG. 2B shows an extension of the binary NVM cell scenario of FIG. 2A, where the voltage distribution graph depicts possible threshold voltage distributions associated with the threshold voltage of a multi-level non-volatile memory cell (“MLC”), wherein one set of vertical lines depicts boundary values correlated with each of the cell's possible Program Verify Threshold Voltages (PV00, PV01, etc . . ) and another set of vertical lines depict boundary values correlated with the Read Verify level of each of the cell's possible Program states (RV00, RV01, etc . . ).
For purposes of producing mass data storage devices, NVM cells are usually organized into and fabricated as part of a large matrix of cells. Depending upon which one of the many known architectures and operating methodologies is used, each cell may be addressable, programmable, readable and/or erasable either individually or as part of a group/block of cells. Most cell array architectures, including virtual ground arrays, which are well known in the field, include the feature of a multiplicity of repeating segments formed into rows and columns. Each array segment may include a cell area formed of four segmented cell bit lines, an even select area, and an odd select area. The even select area may be located at one end of the cell area and may include a segmented even contact bit line and two select transistors connecting the even contact bit line with the even cell bit lines of the segment. The odd select area may be located at the opposite end of the cell area and may include a segmented odd contact bit line and two select transistors connecting the odd contact bit line with the odd cell bit lines of the segment. The array additionally may include one even contact connected to the even contact bit lines of two neighboring even select areas, one odd contact connected to the odd contact bit lines of two neighboring odd select areas and alternating even and odd metal lines connecting to the even and odd contacts, respectively.
Various methods for programming (i.e. injecting charge into the charge storage regions) and/or erasing (i.e. removing charge from a charge storage region) of individual cells within an NVM array are well known. For the most part, the amount of charge stored in a charge storage region of an NVM cell may be increased by applying one or more programming pulses to the cell, while conversely, the amount of charge in the charge storage region of a cell may decrease by applying one or more erase pulses to the gate terminal of an NVM cell, thus forcing the release of trapped charges from the cell's trap region and from the cell's trap interfaces. Alternatively the erase may constitute of injecting charge of opposite polarity rather than a physical removal of charge. For example if the programming is injecting electrons into the traps, the erase may be the injection of holes to the traps. The opposite charges may recombine and or cancel the effect of each other. More specifically, an erase procedure for one or more NVM cells may be characterized by the application of a strong negative voltage pulse to the gates, word lines, of the one or more cells (e.g. −7V), the application of a positive voltage to the drains of the cells (e.g. +3V to +7V) and allowing the sources of the cell to float. Neighboring cells within the same block as the cells being erased, but which are not undergoing erasure (i.e. unselected cells), may receive a positive inhibit voltage on their gate lines, typically between 3 to 5 volts. For cell's being erased, the charges stored in the trap region near the junction, slightly over the channel, are sunk in the drains of the cells being erased (or being recombined with the hole injection).
It should be understood by one of ordinary skill in the art that the preceding and proceeding discussions relating to the operation of a cell also apply to the operation of each charge storage region of a multi-charge storage region device. Multi-charge storage region NVM cells are known in the art and may store two or more logical values, where each logical value may be associated with a different charge storage region, and each charge storage region may be read from a terminal of the device.
Generally, when erasing a cell, one or more of the neighboring cells may also be affected by the erase operation, causing thereto a possible change in their threshold voltage and logical state. This unwanted change in threshold voltage of unselected cells is known in the art as the disturb problem, herein a “disturb”.
In order to the address disturb conditions, some array architectures segment the bit-lines, where each row of the segmented bit-lines is called a “block” and each block typically includes block select transistors to enable the activation of only one block at a time. This feature is particularly important for FLASH electrically erasable, programmable, read only memory (FLASH EEPROM) arrays which pass high voltages along the bit-lines during erase operations. During erase operations, the bit-line voltages may disturb unselected cells. Thus, bit-lines may be segmented into relatively small blocks, thereby isolating blocks being erased from blocks not being erased. However, this solution is very costly in terms of area.
As mentioned above, another method which has been developed in order to mitigate the disturb effect on neighboring cells is the application of an “inhibit voltage” to one or more terminals of the cells not being operated (i.e. erased). Although the application of an inhibit voltage to the terminals of neighboring cells has been found effective in dramatically reducing the erase disturb of the high Vt state, it has been found that two new disturbs may occur. The first erase disturb is the reduction of a programmed Vt, and the 2nd is the increase of the low erased Vt. The change in the threshold voltage of a cell connected to the same bit-line as a cell being erased may result in the change of the state of the cell. Thus, a programmed cell may become erased or an erased cell may become programmed.
The mechanism responsible for the disturb effect on neighboring cells (i.e. connected to the same bit-line having. inhibit WL voltage and floating source) is the current flow through their channel. This current charges the floating source lines, but also create hot electrons in their channel that can be injected into the trapping layer arid increase the Vt of an erased cell. These hot electrons can create holes by impact ionization and the holes may be injected into trapping layer and reduce the Vt of a programmed cell.
Although it would seem plausible to mitigate the above described disturb effect by applying substantially similar voltages to the source and drain bit-lines (i.e. not leaving the source bit-line floating), doing so has been found to have an adverse impact on the efficiency of the erase process. Short channel devices have been found to be susceptible to effects such as punch-through when the potential on the source and drain terminals are both raised during an erase process, and these effects greatly reduce the efficiency of the erase process while greatly increasing the amount of time and current required to achieve a full erase of a cell.
There is a need in the field of NVM array fabrication and operation for an improved method to mitigate neighboring cell disturbs during erase operations.